Elect Design and Analy Engr 4 in Tukwila, WA at Volt

Date Posted: 10/17/2021

Job Snapshot

  • Employee Type:
  • Location:
    Tukwila, WA
  • Duration:
    24 weeks
  • Date Posted:
  • Job ID:
  • Contact Name
    Volt Branch
  • Phone

Job Description

Volt is hiring for an Electrical Design and Analysis Engineer 4 for Aerospace client in Seattle WA.   ** Remote - Can be virtual but possible travel to onsite location as needed.

We are seeking experienced integrated circuit (IC) layout engineers to implement custom analog/mixed-signal circuits in state-of-the-art CMOS (≤22nm) and SiGe semiconductor fabrication processes. The qualified candidate will have experience performing custom IC layout to achieve tight matching, high speed, low noise, and low power consumption. Circuits for custom layout may include analog or digital standard cells, resistors and capacitors, IO cells, ESD structures, and SRAM leaf cells.

Tasks/responsibilities include:
• Working closely with IC / chip design team on block-level and chip-level floor-planning
• Performing cell-level layout, block-level layout, and chip assembly
• Performing physical verification including design rule checks (DRC), layout vs. schematic (LVS) checks, and electrical rule checks (ERC)
• Perform / support parasitic extraction (PEX) and analysis
• Drive continued improvement of layout practices and procedures


• This position requires the ability to obtain a US Security Clearance for which the US Government requires US Citizenship.
• Bachelor, Master or Doctorate degree from an accredited course of study, in engineering, computer science, mathematics, physics or chemistry
• 6+ years of experience in full-custom analog/mixed-signal IC layout
• Thorough understanding of industry-standard electronic design automation (EDA) tools for IC layout and physical verification – e.g. those from Cadence, Mentor Graphics, and Synopsys
• Experience with standard cell development and/or familiarity with structured, pitched, or arrayed layout
• Knowledge of performance analog and high-power layout techniques
• Experience exercising and debugging the IC verification flow (DRC, LVS, XOR, PEX, etc.)
• Demonstrated successful IC designs implemented in advanced commercial semiconductor fabrication process technologies – e.g.. <22nm FinFET), silicon-on-insulator (SOI), and/or silicon germanium (SiGe) processes.
• Experience with layout techniques for managing IR drop, RC delay, electromigration, self-heating and coupling capacitance

***Preferred Qualifications:
• Experience with Radiation-Hardened By Design (RHBD) layout techniques
• Experience with scripting to automate IC layout (e.g. SKILL, Perl, Python)
• Experience with experimental process technologies (e.g. Gate-all-around FETs (GAAFETs))
• Active security clearance

Volt is an equal opportunity employer