ASIC FEINT (Front End Integration) Design Engineer (Markham, ON) in Markham at Volt

Date Posted: 7/26/2019

Job Snapshot

  • Employee Type:
  • Location:
  • Job Type:
  • Duration:
    48 weeks
  • Date Posted:
  • Job ID:
  • Pay Rate
    $60.46 - $80.61/Hour
  • Contact Name
    Volt Branch

Job Description


We are looking to hire an ASIC FEINT (Front End Integration) Design Engineer for our client in the Semiconductor industry in Markham, ON for approximately a 12-month assignment with the possibility of extension, through our Company Volt Workforce Solutions Canada.

Job Description:

  • Job Title: ASIC FEINT Design Engineer 
  • Client: A Semiconductor Company
  • Employer: Volt Workforce Solutions Canada
  • Location: Markham, Ontario, CAN, L3T7X6
  • Term: Approximately 12-month’s assignment with the possibility of extension
  • Hours per week: 37.5 Hours per week.
  • Pay Rate: $60.46/hr - $80.61/hr (T4) depending on experience + benefits available

*Note: Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information*

*Candidates must be eligible to work in Canada without employment sponsorship*

 Key Responsibilities: 
• Synthesis, constraints development and ECO of digital ASIC design blocks. 
• Understanding of digital design static timing analysis. 
• Understanding of digital design power, performance, area trade-off analysis. 
• Ability to read and perform modifications to RTL in order to effect Improvement in power, performance, area metrics. 
• Implement and verify ECO’s using manual and/or tool automated flows (Conformal ECO). 
• Basic familiarity with digital design simulation and debug. 
• Occasional creation of utility software or scripts (C++, Perl, Python, TCL, etc.) 
• Co-coordinating synthesis and constraints development and verification for multiple design blocks. 
• Debug of constraints compatibility issues between IP and SOC. 
• Use standard design verification tools such as CDC, LINT, Power Analysis, Synthesis, Formal Verification, etc. 

Preferred Experience: 
• 3+ years RTL coding and verification experience 
• 3+ years of netlist synthesis, constraints development and timing analysis experience 
• Experience with ASIC ECO implementation and verification methodologies 
• Understanding of post place and route timing analysis and timing closure 
• Excellent knowledge of Verilog, C, C++ and common scripting languages (Make, TCL, 
 Perl, Python, C, C++, etc) 
• Experience with standard bus/interface protocols (AMBA, AXI, AHB) 
• Strong understanding of digital design and logic synthesis 
• Prior experience with simulation, emulation and FPGA prototyping 
• Strong analytical/problem solving skills and pronounced attention to details. 
• Must be a self-starter, and able to independently drive tasks to completion. 
• Strong interpersonal and communication skills 

• Bachelor or Masters degree in Electrical or Computer Engineering 

Volt is an Equal Opportunity employer.